5:02 Christian Fabre, CEA - Welcome from the RISC-V Summit Europe Steering Committee RISC-V International
5:03 Daniel Müller-Gritschneder & Teresa Cervero - RISC-V Summit Europe Program Overview RISC-V International
14:56 Mark Himelstein, RISC-V International - RISC-V: The Road Ahead and Technical Update RISC-V International
15:44 Rick O’Connor - Commercial Adoption of CORE-V Open-Source RISC-V Cores - Lessons Learned RISC-V International
19:05 Balaji Baktha - Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive & More RISC-V International
15:18 Jon Taylor - The RISC-V Verification Ecosystem with Open Standards and Commercial Tools RISC-V International
10:34 Brett Cline, Codasip - RISC-V customization, HW/SW co-optimization, and custom compute RISC-V International
17:04 Daniele Rossi, University of Pisa - HW-SW Interface for RAS in RISC-V Architectures RISC-V International
15:36 Roger Espasa, Semidynamics - Semidynamics Highly Configurable OOO Vector Unit RISC-V International
14:21 Michael Gielda - RISC-V and Antmicro’s visual system designer: Everything everywhere all at once RISC-V International
15:20 Anthony Zgheib - Enhancing the RISC-V Trace Encoder to Verify the Control-Flow and More RISC-V International
16:03 Franz Fuchs - Mitigating Transient-Execution Attacks with CHERI Compartments RISC-V International
13:55 Jimmy Le Rhun - Safe, Secure and Reliable Computing with the NOEL-V Processor RISC-V International
