30:20 Philipp Tomsich, VRULL GmbH - SW-driven evolution of a uniquely modular and extensible ISA RISC-V International
16:38 Wei-han Lien, Tenstorrent - A High-Fidelity Flow for High-Performance RISC-V CPU Design from Scratch RISC-V International
13:16 David Mallasén Quintana - PERCIVAL: Integrating Posit and Quire Arithmetic into the RISC-V Ecosystem RISC-V International
30:48 Alex Bradbury, Igalia - Developments in LLVM-based toolchains and tooling for RISC-V RISC-V International
16:15 Stanislaw Kaushanski - Automated Cross-level Verification Flow of a Highly Configurable RISC-V Core RISC-V International
17:40 Andrei Warkentin - Multi-ISA Firmware Compatibility - Bringing RISC-V and IHV Ecosystems Together RISC-V International
16:41 Luca Lingardo-Implementation of an Edge-Computing architecture based on a RISC-V core for RFID Comms RISC-V International
12:09 Guy Lemieux - From CCX to CIX: A Modest Proposal for (Custom) Composable Instruction eXtensions RISC-V International
12:27 Tariq Kurd-RISC-V code-size reduction w/ Zc extensions and dictionary compression custom instruction RISC-V International
14:10 Andrei Ivanov- RIVETS: An Efficient Training and Inference Library for RISC-V with Snitch Extensions RISC-V International
17:48 Gregory Chadwick - Building commercially relevant open source silicon: The many aspects of Ibex RISC-V International
12:14 Marton Bognar - Proteus: An Extensible RISC-V Core for Hardware Extensions RISC-V International
14:32 Thomas Benz, ETH Zürich - Puma: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS RISC-V International
9:43 Bruno Sá, University Of Minho - RISC-V Virtualization: A Case Study on the CVA6 RISC-V International
14:32 Yifei Zhu|GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations RISC-V International
8:59 Calista Redmond, RISC-V International & Christian Fabre, CEA & more - Closing & Announcements RISC-V International
