13:58 Karol Gugala, Antmicro - Bare Metal AI Runtime Deployment and Analysis for a RISC-V Accelerator RISC-V International
11:41 Chris Morrison, Agile Analog - Digitally Wrapped Analog IP Subsystem for RISC-V Applications RISC-V International
9:58 Massimiliano Giacometti, OpenHW Group - OpenHW CVA6 Linux-capable, dual-core processor on Genesys2 RISC-V International
5:16 Mikael Carmona, CEA - VASCO 2, an ASIC to Highlight the Latest Innovations in Security of Component RISC-V International
15:21 Roger Espasa, Semidynamics - Semidynamics Vector Unit Performance Demonstration RISC-V International
13:20 Warren Chen, Andes Technology Andes AI Runs Everywhere with DSP/Vector/NN Libraries and AndesClarity RISC-V International
10:18 Brian Colgan, Microchip - Introducing the PolarFire® SoC Smart Embedded Vision Kit RISC-V International
11:14 Jan Andersson, Frontgrade Gaisler - Designing a RISC-V SoC with the NOEL-V Processor and more. RISC-V International
14:34 Dr. Ari Kulmala, TII - Secure RISC-V for Flight controller and Mission Computer RISC-V International
