5:00

Opening remarks at TASER 2021, by Dan Page, Bristol University

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28:12

An overview of security topics within RISC-V, by Helena Handschuh

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22:04

RISC-V cryptography extensions: current status and future plans, Ben Marshall

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25:28

Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs, Barbara Gigerl,

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25:59

Can we solve timing side-channels in the CPU?, Ronan Lashermes, INRIA

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23:40

Current status of RISC-V security mechanisms, Nick Kossifidis, FORTH

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28:24

CHERI and CHERI-RISC-V, by Simon Moore, University of Cambridge

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1:07

Closing remarks at TASER 2021, by Dan Page of Bristol University

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