9:29

[PLARCH23] Semi-Automated Translation of a Formal ISA Specification to Hardware

ACM SIGPLAN

11:42

[PLARCH23] Leakage models are a leaky abstraction (...)

ACM SIGPLAN

17:44

[PLARCH23] Hardware-Software Codesign for Mitigating Spectre

ACM SIGPLAN

12:27

[PLARCH23] Hardware Verification of Timing Side Channel Freedom in the Spectre Era

ACM SIGPLAN

9:41

[PLARCH23] Tags: A Framework for Distributed Event Ordering

ACM SIGPLAN

16:00

[PLARCH23] Stellar: A DSL to Build and Explore Sparse Accelerators

ACM SIGPLAN

12:29

[PLARCH23] PEak: A Single Source of Truth for Hardware Design and Verification

ACM SIGPLAN

10:28

[PLARCH23] Challenges with Hardware-Software Co-design for Sparse Machine Learning on (...) Dataflow

ACM SIGPLAN

14:49

[PLARCH23] They're the same picture: a software-verification flow adapted for hardware verification

ACM SIGPLAN

17:08

[PLARCH23] Design for Hardware Memory Model Verification

ACM SIGPLAN

9:59

[PLARCH23] Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware

ACM SIGPLAN

11:57

[PLARCH23] NFC:Next-generation Formal verification for high performance Caches

ACM SIGPLAN

9:37

[PLARCH23] Sandia's Formal Hardware Design and Verification, Present and Future

ACM SIGPLAN

9:16

[PLARCH23] Silver Oak: Hardware Software Co-Design and Co-Verification in Coq

ACM SIGPLAN

11:44

[PLARCH23] Novel Numerical Hardware Design Methodology - From machine readable spec to optimized RTL

ACM SIGPLAN

16:24

[PLARCH23] Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design

ACM SIGPLAN

9:30

[PLARCH23] New Embedded DSLs for Hardware Design and Verification

ACM SIGPLAN

13:56

[PLARCH23] Fearless Hardware Design

ACM SIGPLAN

12:02

[PLARCH23] Library-based Compartmentalisation on CHERI

ACM SIGPLAN

8:18

[PLARCH23] Non-Newtonian Hardware Design for Longevity

ACM SIGPLAN

9:50

[PLARCH23] On the Generality of Matrix Multiplication

ACM SIGPLAN

8:16

[PLARCH23] ChatGPT, Make a Secure Malloc for me

ACM SIGPLAN